A flash or block erase memory (flash memory), such as, Electrically Erasable Programmable Read-Only Memory (Flash EEPROM), includes an array of cells, which can be independently programmed and read. The size of each cell and thereby the memory as a whole are made smaller by eliminating the independent nature of each of the cells. As such, all of the cells are erased together as a block.
A memory of this type includes individual Metal-Oxide Semiconductor (MOS) memory cells that are field effect transistors (FETs). Each FET, or flash, memory cell includes a source, drain, and control gate to which various voltages are applied to program the cell with a binary 1 or 0, or erase all of the cells as a block. The flash memory cell provides for nonvolatile data storage.
A typical configuration of an array of flash memory cells includes rows and columns of flash memory cells. The array is supported by word lines and bit lines, wherein the word lines are coupled to gates of flash memory cells, and the bit lines are coupled to drains. The sources of the flash memory cells are commonly coupled together.
In a dual bit flash memory cell, the flash memory cell stores data by holding charge within an oxide-nitride-oxide (ONO) layer. The charge storage element within the ONO layer allows electrons to be stored on either side of the flash memory cell. As a result, the basic memory cell behaves as two independent conventional memory cells. In a write or programming operation, charge can be placed on the nitride layer through hot electron injection. In addition, hole injection can be typically used for erasing the flash memory cell through the neutralization of charge in the nitride.
A dual bit flash memory device contains two bits. The bit that is selected during a “read” operation has the bit line closest to it assigned as the source. To program the selected bit, a charge may be injected on the source side. The bit that is at the source side (selected) during a “read” operation is known as the “normal” bit. The bit that is at the drain side (not selected) during a read operation is referred to as the complementary bit. There are four states defined for a dual bit cell: a “11” state in which both bits are erased, or in which there is no charge in the cell; a “00” state in which both the bits are programmed; a “01” state in which one bit is programmed and one bit is erased and the selected bit is programmed; and a “10” state in which one bit is programmed and one bit is erased and the selected bit is erased.
Prior Art FIGS. 1A–1D are cross sectional diagrams illustrating the operation of non-volatile dual bit flash memory cells. These figures illustrate the programmed and erased states for a normal bit (the bit that is at the source side in a read operation) and a complementary bit (the bit that is at the drain side in a read operation) in a dual bit flash memory cell. Prior Art FIG. 1A illustrates a dual bit flash memory cell 100a in which a charge 110 is held in the source side 125 of ONO 115. This is a “01” state and represents a cell in which the normal bit is programmed. Channel 120 is blocked by charge 110 and current does not flow from the source side 125 to drain side 130. Whether the cell is programmed (channel blocked) or erased (channel not blocked and current flowing) is determined by the state of the normal bit. (Note that the bit to be read, the normal bit, is defined by the role of the bit line adjacent to it. The normal bit will be the bit adjacent to the source line. The complementary bit will be adjacent to the drain. The roles of the bit lines may change, in which case, in a given dual bit memory cell, either bit may function as a normal bit and, accordingly, as a complementary bit.)
Prior Art FIG. 1B represents a state “11” in which there is no charge present. Therefore both the normal bit (adjacent to source 125) and the complementary bit are erased and the channel 120 is formed, allowing current to flow from source 125 to drain 130.
Prior Art FIG. 1C represents state “10” in which the complementary bit holds charge 140 on the drain side of ONO 115. In this state the channel 120 is formed and current flows from source 125 to drain 130. This state is considered an erased state since there is no charge on the normal bit at the source side.
A failure in dual bit flash memory can result from a broadening of the charge 140 on the complementary bit. This broadening may occur as a result of over programming the complementary bit. This broadening effect results in a reduction of current in channel 120 that, in turn, increases the threshold voltage for state “10”. There is a required window between the threshold voltage for a programmed state (normal bit charged) and an erased state (normal bit erased) which, if compromised, can result in a read failure. This read failure is due to the inability to distinguish between a “0” and a “1” because of the increase in threshold voltage due to the broadening of the charge 140 at a programmed complementary bit. This effect is known as “complementary bit disturbance”.
Prior Art FIG. 1D represents state “00” in which both the bit holding charge 110 and the bit holding charge 140 are programmed. The channel 120 is blocked by charge 110 and no current flows.
Prior Art FIG. 2 is a graph 200 illustrating complementary bit disturbance in non-volatile dual bit flash memory cells. In graph 200, the two bits in the dual bit memory cell undergo cycling of programming and erasure. The cycling begins with the “11” state in which both bits are erased. Next, a first one of the bits is programmed until its threshold voltage (Vt) becomes higher than the target level of threshold voltage for programming. Then, Vt for each bit is measured. The relative Vt for the first programmed bit is represented by NB_PRG 210, showing the “01” state of the cell. The relative Vt for the second bit, which is still in an erased state, is represented by CB_PRG 230, showing the “10” state of the cell.
After the Vt is measured, the second bit is programmed until its Vt reaches the target level for programming and the cell obtains a “00” state (not represented on graph 200). Next, both bits are erased until their Vt falls below the target level for erasure and the Vt of each bit is again measured. NB_ERS 220 represents the relative Vt for the first programmed bit, and CB_ERS 240 represents the relative Vt for the second programmed bit. Since both bits are erased, both NB_ERS 220 and CB_ERS 240 are regarded as a “11” state of the cell. After erasure, the first bit is selected and programmed again as before and the process is repeated to generate multiple cycles of programming and erasure.
The charge on the complementary bit (the bit not being read) may broaden and reduce the current flow which, in turn, can cause an increase in the Vt causing complementary bit disturbance. This can be seen in the data points plotted for CB_PRG 230. The arrow 250 indicates the relative value of a design Vt window that is desirable for being able to distinguish between a programmed and an erased state. Arrow 260 indicates the relative value of the actual Vt window, which can be seen to be compromised by the complementary bit disturbance at CB_PRG 230.